Significant research and development efforts are currently directed towards designing and manufacturing nanoscale electronic devices, including nanoscale memories. Nanoscale electronics promise a number of advantages over microscale, photolithography-based electronics, including significantly reduced features sizes and the potential for self-assembly and for other relatively inexpensive, non-photolithography-based fabrication methods. However, the design and manufacture of nanoscale electronic devices present many new problems that need to be addressed prior to large-scale commercial production of nanoscale electronic devices and incorporation of nanoscale electronic devices into microscale and larger-scale systems, devices, and products.
Nanoscale memory arrays are possible candidates for relatively near-term commercialization. Nanoscale memories can be fabricated as nanowire crossbars with hysteretic-resistors nanowire-crossbar junctions. Relatively large voltages can be applied to a given nanowire-crossbar junction to reversibly configure the given nanowire-crossbar junction in a high-resistance state or low-resistance state, the particular resistance state obtained depending on the polarity of the applied voltage. Relatively lower voltages can be applied to a given nanowire-crossbar junction to read the resistance state of the given nanowire-crossbar junction without changing the resistance state. However, application of voltages even greater in magnitude than the voltages used to reversibly configure nanowire-crossbar junctions can irreversibly destroy the nanowire-crossbar junctions to which the greater voltages are applied. Each nanowire-crossbar junction serves as a single-bit memory element, storing a binary value “0” or “1” as a high-resistance or low-resistance state, respectively. It is difficult, however, to directly access the nanowires from which nanoscale array memories are constructed using convention microelectronic signal lines and logic. Instead, the nanowires are addressed through selective interconnections to microscale output signal lines of mixed microscale/nanoscale encoder-demultiplexers. A nanowire address input to an encoder-demultiplexer via microscale address lines is transformed into a pattern of addressed-nanowire selection voltages output by the encoder to microscale output signal lines of the encoder-demultiplexer. Selection of the two nanowires that cross at a particular nanowire-crossbar junction by two encoder-demultiplexers results in applying a defined voltage to the nanowire-crossbar junction selected by input of two nanowire addresses to the two encoder-demultiplexers. Because of the need to apply a WRITE-access voltage of a magnitude in a voltage-magnitude range between a minimum resistance-state-changing threshold voltage and a junction-destroying threshold voltage to the selected nanowire-crossbar junction, while applying voltages of magnitudes less than minimum resistance-state-changing threshold voltage to all other, non-selected nanowire-crossbar junctions in order to change the information content of the selected nanowire-junction, the addressed-nanowire selection voltages output by the encoder-demultiplexers need to result in large separation between the voltage applied to a selected nanowire-crossbar junction and voltages applied to all other, non-selected nanowire-crossbar junctions or, in other words, to reasonably large voltage margins for WRITE-access operations. For this reason, designers and manufacturers of nanoscale memory arrays have recognized the need for finding effective nanowire addressing schemes, and for building encoder-demultiplexers based on these addressing schemes, in order to provide sufficient voltage margins for reliably accessing individual junctions within a nanowire crossbar.